1. Field of the Invention
The present invention relates generally to a computer implemented method, data processing system, and computer program product for scheduling one or more threads to one or more physical processors among a pool of physical processors. More specifically, the present invention relates to assigning a virtual machine or partition to virtual processors in a cache efficient manner.
2. Description of the Related Art
Modern operating systems use a page-based virtual memory system where virtual memory is mapped to real memory in units of pages. The amount of available memory is finite, and the memory is subdivided into multiple individual pages of a pre-established size. Thus, a memory page is a unit of memory allocation used to virtualize physical memory.
Multiple core microprocessors host multiple physical processors. A physical processor is a collection of circuits that sequentially executes program instructions to manipulate data. A physical processor or core may include an arithmetic logic unit (ALU) as well as one or more registers. The design feature of multiple core microprocessors enables modern computers to process more data than single core microprocessors of a generation ago. Many multiple core microprocessors rely on a hypervisor to allocate resources to various running processes. A hypervisor is a software component that assigns virtual resources to available physical resources.
A physical microprocessor may contain multiple hardware threads of execution. A hardware thread may support the operation of a virtual machine. A hardware thread may support virtualization. A partition is an environment that executes upon virtual resources that have been abstracted from physical resources by a Hypervisor. A virtual machine simulates the hardware platform on which the partition runs. A partition may include the features of storage, system call interfaces, code interpreters, garbage collectors, and I/O ports, among other interfaces. A partition may also be described as a virtual machine. Each partition contains one or more virtual processors. The assignment of a virtual processor to a physical processor is called dispatching. Thus, a hypervisor dispatches a virtual processor of a partition to a physical processor.
Attendant with dispatching, the hypervisor selects available virtual processors from among several partitions that are referenced by a run queue. The time that a virtual processor waits in the run queue is the dispatch latency. A ready to run virtual processor is said to be runnable. A data processing system may apportion timeslices in arbitrary time units, but usually time segments of less than 10 milliseconds. During an interval where a first virtual processor finishes its allocated time slot and a second virtual processor begins its allocated time slot, the hypervisor performs a context switch. The virtual processors can be from different partitions. During the context switch, one or more hardware translation mechanisms keep each partition from directly accessing each other's memory. However, as the second virtual processor runs, it will naturally displace the contents in cache used by the first virtual processor.
Unfortunately, the reduced effectiveness of the cache due to context switching slows the rate of instructions through the microprocessor, as references for instructions and data now more frequently must be accessed from memory. In addition, where two virtual machines run distinct instances of a common operating system, the virtual machines will rely on identical code to perform their respective functions. Such identical code may be within the memory page, as allocated by the Hypervisor. Consequently, running virtual processors for different partitions that share common memory can reduce the amount of cache interference between partitions.
Unfortunately, prior art architectures cannot determine an extent to which a physical processor assignment will avail itself to reduced cache contention overhead. Moreover, the prior art architectures do not utilize knowledge of commonality of memory pages in cache to guide assignment of dispatching virtual processors to physical processors.